1. Field of the Invention
The present invention relates to a glitch eliminating circuit. More particularly, the present invention relates to a deglitch circuit.
2. Description of Related Art
In a high-speed transmission system and interface, for example, a universal serial bus (USB), a peripheral component interconnect express (PCI-E) or a serial advanced technology attachment (SATA), a receiver thereof generally determines whether a received data signal is an effective data or a noise through a high-speed comparator. If differential amplitude of the data signal is greater than a reference voltage, and the comparator determines the data signal is the effective data, the comparator can output “0” to represent that the data signal is the effective data. Conversely, if the differential amplitude of the data signal is less than the reference voltage, and the comparator determines the data signal is the noise, the comparator can output “1” to represent that the data signal is the noise.
FIG. 1 is a schematic diagram illustrating generation of a glitch waveform. Referring to FIG. 1, in case of an ideal circumstance, a rising and a falling time of a differential signal pair (data signal) Dp and Dm transmitted by a transmitter are all regarded to be zero, so that the differential amplitude remains greater than the reference voltage during a transition period of the data signal, and the comparator determines the data signal is the effective data. Therefore, the comparator can output an ideal waveform Sideal of FIG. 1. However, in case of an actual high-speed transmission, the rising and the falling time of the data signal (the differential signal pair Dp and Dm) transmitted by the transmitter cannot approach to zero; the longer the transmission cable is, the more moderate the waveform of the data signal received by a receiver tends to be. During a voltage level switch process caused by logic transition (for example, logic 0 is transited to be logic 1) of the data signal Dp/Dm, since a difference (i.e. the differential amplitude during the switch process) of the data signal Dp/Dm at a rising edge and a falling edge can be temporarily less than the reference voltage, an actual output waveform SReal of the comparator may have glitch during the voltage level switch process of the data signal Dp/Dm. Such phenomenon can cause errors of data received by the transmission system.
Therefore, an output of such high-speed comparator is generally processed by a deglitch circuit to eliminate the undesired glitch. A commonly used deglitch circuit is shown as FIG. 2A, FIG. 2A is a schematic diagram illustrating a conventional deglitch circuit. Referring to FIG. 2A, a delay circuit 201 of the deglitch circuit 200 first delays the glitch to generate a delay signal, and then a logic operation is performed to the delay signal and an original output signal of the comparator (not shown) by an AND gate 202 to eliminate the glitch.
FIG. 2B is a schematic diagram of signal waveforms of FIG. 2A. Referring to FIG. 2A and FIG. 2B, after the AND gate 202 performs the logic operation to the output signal SQ of the comparator and the delay signal SQD of the delay circuit 201, the glitch is removed from an output waveform SDG of the AND gate 202. However, such method has two shortages, one is that a glitch width that can be eliminated by the deglitch circuit 200 is limited, and when the glitch width is too broad, regardless of how the output signal SQ being delayed, the output signal SQ and the delayed signal SQD cannot be totally interlaced, so that the possibly appeared glitches cannot be totally removed. The second shortage is that the delay time of the delay circuit can be drifted along with a fabrication process. In case of different process corners, the delay time can be different, so that the glitch width that can be eliminated is further limited. The faster the operation speed of the transmission circuit is, and the longer the transmission cable is, the higher occupation ratio the rising time and the falling time of the data signal in a cycle is. Therefore, a broader glitch is generated, and the deglitch circuit 200 is no longer applicable.
Another commonly used method is to apply a peak detector of FIG. 3A. FIG. 3A is schematic diagram of a conventional peak detector. FIG. 3B is a schematic diagram illustrating signal waveforms of FIG. 3A. Referring to FIG. 3A and FIG. 3B, a principle of the peak detector 300 is as follows. According to uni-directionality of diodes D1 and D2, when the data signals Dp and Dm are greater than conducting voltages of the diodes D1 and D2, a capacitor C is charged, so that a voltage level of the capacitor C can be increased. When the voltage levels of the data signals Dp and Dm are switched, since the diodes D1 and D2 are unidirectional, the capacitor C is not discharged towards an input terminal of the peak detector 300, but can only be discharged through a tiny discharge current source IL. Therefore, as long as the data signal Dp/Dm has data, a voltage of an output signal Out can be maintained above a voltage Va.
When the data signal Dp/Dm has no data, the voltage of the output signal Out is pulled to “0” through the discharge current source IL, so as to determine the data signal Dp/Dm has no data. The peak detector 300 has two shortages, one is that a propagation delay of such circuit is related to an amplitude of an input signal (i.e. the data signal Dp/Dm), the smaller the amplitude of the output signal is, the smaller the charging current of the capacitor that passes through the diodes D1 and D2 is, and the longer the propagation delay that the output signal is changed from “0” to “1” is. Namely, a time for the voltage of the output signal Out being charged from a low voltage level to a high voltage level is prolonged. Comparatively, the greater the amplitude of the output signal is, the longer the propagation delay that the output signal is changed from “1” to “0” is. Namely, a time for the voltage of the output signal Out being discharged from the high voltage level to the low voltage level is prolonged. Therefore, the peak detector 300 cannot effectively control the propagation delay.
The second shortage is that only non-ideal diodes can be used for an actual implementation, and if a MOS transistor is applied to implement the uni-directionality of the diode, a tiny inverse current still exists, and the inverse current can result in a fact that a direct current (DC) transition point cannot be accurately controlled. In a general is high-speed transmission system, there have specifications of the DC transition point and an alternating current (AC) transition point. If the peak detector 300 is applied to avoid the glitch, a design of the DC transition point and the AC transition point is difficult. Moreover, the transmission system has a specification of the propagation delay, and the time of the propagation delay cannot be accurately controlled when the peak detector 300 is used. Therefore, though application of the peak detector 300 can eliminate the glitch, design of other specifications of the transmission system is influenced, so that the application of the peak detector 300 is limited.